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preliminary technical data sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processor adsp-21261 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bi t floating-point processor optimized for high precision signal processing applications the adsp-21261 is available with a 150 mhz (6.67 ns) core instruction rate. the adsp-21261 sharc processor is code compatible with all other sharc processors single-instruction multiple-data (simd) computational archi- tecturetwo 32-bit ieee floating-point/32-bit fixed- point/40-bit extended precisio n floating-point computa- tional units, each with a multiplier, alu, shifter, and register file high bandwidth i/o a parallel port, spi port, four serial ports, digital audio interface (dai), and jtag dai incorporates two precision clock generators (pcgs), an input data port (idp) which includes the parallel data acquisition port (pdap), and three programmable timers, all under software control through the signal routing unit (sru) on-chip memory1m bit of on-chip sram and a dedicated 3m bit of on-chip mask-programmable rom six independent synchronous serial ports provide a variety of serial communication protocols including tdm and i 2 s modes for complete ordering information, see ordering guide on page 44 . figure 1. functional block diagram addr data px regi ster 6 jtag test & emulation 20 3 serial ports (4) input data ports (8) parallel data acquis ition p ort timers (3) si gnal ro u ti ng unit precisi on clo ck generators (2) digital audio interface 3 16 address/ data bus/ gpio control/gpio parallel port iop registers (memory mapped) co n tr ol , status, & data buffers 4 sp i po rt (1) dma controller 18 channels 4 gpio flags/ irq/timex p i/o processor process ing element (p ey) proces sing el eme nt (pex) timer instruction ca c h e 32 48 -bit dag1 8 4 32 da g2 8 4 32 32 pm address bus dm address bus pm data bus dm data bus 64 64 core processor pro gram sequencer sram 0.5m bit rom 1. 5m bit addr data dual ported memory block 0 dual ported memory bl o ck 1 s iod (32) ioa (18) 32 sram 0.5 m bit rom 1. 5m bit
rev. prb | page 2 of 44 | june 2004 adsp-21261 preliminary technical data key features at 150 mhz (6.67 ns) core instruction rate, the adsp-21261 operates at 900 mflops peak performance 300 mmacs sustained performance at 150 mhz super harvard architecturet hree independent buses for dual data fetch, instruction fetch, and nonintrusive, zero- overhead i/o 1m bit on-chip dual-ported sram for simultaneous access by core processor and dma 3m bit on-chip dual-ported mask-programmable rom dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution each processing element executes the same instruction, but operates on different data parallelism in buses and computational units allows: sin- gle cycle executions (with or without simd) of: a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained 2.4g byte/s bandwidth at 150 mhz core instruction rate. in addition, 600m byte/sec is available via dma accelerated fft butterfly computation through a multiply with add and subtract instruction dma controller supports: 18 zero-overhead dma channels for transfers between adsp-21261 internal memory and serial ports (12), the input data port (idp) (4), spi- compatible port (1), and the parallel port (1) 32-bit background dma transfers at core clock speed, in par- allel with full-speed processor execution asynchronous parallel/external port provides: access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 50m byte per sec transfer rate for 150 mhz core rate external memory access in a dedicated dma channel 8- to 32-bit and 16- to 32-bit word packing options programmable wait state options: 2 to 31 cclk digital audio interface (dai) includes four serial ports, two precision clock generators, an input data port, three pro- grammable timers and a signal routing unit serial ports provide: four dual data line serial ports that operate at up to 37.5m bit/s for a 150 mhz core on each data line each has a clock, frame sync, and two data lines that can be con- figured as either a receiver or transmitter pair left-justified sample pair and i 2 s support, programmable direction for up to 24 simultaneous receive or transmit channels using two i 2 s compatible stereo devices per serial port tdm support for telecommunications interfaces including 128 tdm channel support for tele phony interfaces such as h.100/h.110 up to four tdm streams, eac h with 128 channels per frame companding selection on a per channel basis in tdm mode input data port provides an additional input path to the dsp core configurable as either eight channels of i 2 s or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port supports receive audio channel data in i 2 s, left-justified sample pair, or right-justified mode signal routing unit provides configurable and flexible connections between all dai components, four serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 sru i/o pins (dai_px) serial peripheral interface (spi)provides: master or slave serial boot through full-duplex operation master-slave mode multi-master support open drain outputs programmable baud rates, clock polarities, and phases 3 muxed flag/irq lines 1 muxed flag/timer expired line rom based security features: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software multiplier ratios jtag background telemetry for enhanced emulation features ieee 1149.1 jtag standard test access port and on-chip emulation dual voltage: 3.3 v i/o, 1.2 v core available pakages: 136-ball bga, 136-ball lead-free bga, 144-lead lead-free lqfp code-compatible with all previous sharc processors pin-compatible with adsp-2126x and adsp-2136x processors
adsp-21261 preliminary technical data rev. prb | page 3 of 44 | june 2004 table of contents general description ................................................. 4 adsp-21261 family core architecture .. .................... 4 simd computational engine ............................... 4 independent, parallel computation units ................ 5 data register file ............................................... 5 single-cycle fetch of instruction and four operands ...................................................... 5 instruction cache .............................................. 5 data address generators with zero-overhead hardware circular buffer support ...................... 5 flexible instruction set ....................................... 6 adsp-21261 memory and i/ o interface features ......... 6 dual-ported on-chip memory ............................. 6 dma controller ................................................ 6 digital audio interface (dai) ............................... 6 serial ports ....................................................... 6 serial peripheral (compatible) interface .................. 8 parallel port ..................................................... 8 timers ............................................................ 8 rom based security ........................................... 8 program booting ............................................... 8 phase-locked loop ............................................ 8 power supplies .................................................. 8 target board jtag emulator connector .................... 9 development tools ............................................... 9 designing an emul ator-compatible dsp board (target) ........................................... 10 additional information ......................................... 10 pin function descriptions ........................................ 11 address data pins as flags .................................. 14 boot modes ........................................................ 14 core instruction rate to clkin ratio modes ............. 14 address data modes ............................................. 14 adsp-21261 specifications ....................................... 15 recommended operating conditions ....................... 15 electrical characteristics ........................................ 15 absolute maximum ratings ........................ 15 esd sensitivity .............................................. 16 timing specifications ........................................... 16 power-up sequencing ....................................... 18 clock input ..................................................... 19 clock signals ................................................... 19 reset ............................................................. 20 interrupts ....................................................... 20 core timer ..................................................... 20 timer pwm_out cycle timing ......................... 21 timer wdth_cap timing ............................... 21 dai pin to pin direct routing ............................ 22 precision clock generator (direct pin routing) ...... 23 flags ............................................................. 24 memory readCparallel port ................................ 25 memory writeparallel port ............................. 27 serial ports ..................................................... 29 input data port (idp) ....................................... 32 parallel data acquisition port (pdap) .................. 33 spi interfacemaster ....................................... 34 spi interfaceslave .......................................... 35 jtag test access port and emulation .................. 36 output drive currents ......................................... 37 test conditions .................................................. 37 capacitive loading .............................................. 37 environmental conditions .................................... 38 thermal characteristics ........................................ 38 136-ball bga pin configurations ............................... 39 144-lead lqfp pin configurations .. .......................... 42 package dimensions ............................................... 43 ordering guide ..................................................... 44
rev. prb | page 4 of 44 | june 2004 adsp-21261 preliminary technical data general description the adsp-21261 sharc dsp is a member of the simd sharc family of dsps featuring analog devices super har- vard architecture. the adsp-21261 is source code compatible with the adsp-21160 and adsp- 21161 dsps as well as with first generation adsp-2106x shar c processors in sisd (sin- gle-instruction, single-data) mode. like other sharc dsps, the adsp-21261 is a 32-bit/40-bit fl oating-point processor opti- mized for high precision signal processing applications with its dual-ported on-chip sram, mask-programmable rom, multi- ple internal buses to eliminate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the adsp- 21261 uses two computational unit s to deliver a 5 to 10 times performance increase over the adsp-2106x on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the adsp-21261 dsp achi eves an instruction cycle time of 6.67 ns at 150 mhz. with its simd computational hard- ware, the adsp-21261 can perf orm 900 mflops running at 150 mhz. table 1 shows performance benchm arks for the adsp-21261. the adsp-21261 continues sharc s industry leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include 1m bit dual -ported sram memory, 3m bit dual-ported rom, an i/o pr ocessor that supports 22 dma channels, six serial port s, an spi interface, external parallel bus, and digital audio interface (dai). the block diagram of the adsp-21261 on page 1 illustrates the following architec tural features: two processing elements, each containing an alu, multi- plier, shifter, and data register file data address generators (dag1, dag2) program sequencer with instruction cache pm and dm buses capable of supporting four 32-bit data transfers between memory an d the core at every core processor cycle three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities on-chip dual-ported sram (1m bit) on-chip dual-ported mask-programmable rom (3m bit) jtag test access port the block diagram of the adsp-21261 on page 1 , illustrates the following architectural features: 8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals dma controller six full duplex serial ports spi compatible interface digital audio interface that includes two precision clock generators (pcg), an input da ta port (idp), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (sru) figure 2 on page 5 shows one sample conf iguration of a sport using the precision clock generator to interface with an i 2 s adc and an i 2 s dac with a much lower jitter clock than the serial port would generate itself. many other sru configurations are possible. adsp-21261 family core architecture the adsp-21261 is code compatible at the assembly level with the adsp-21266, adsp-21160 and adsp-21161, and with the first generation adsp-2106x sharc dsps. the adsp-21261 shares architectural featur es with the adsp-2126x and adsp-2116x simd sharc family of dsps, as detailed in the following sections. simd computational engine the adsp- contains two co mputational processing ele- ments that operate as a single-instruction multiple-data (simd) engine the processing elements are referred to as pe and pe and each contains an alu, multiplier, shifter, and reg- ister file pe is always active, and pe may be enabled by setting the pee mode bit in the mode register when this mode is enabled, the same instru ction is executed in both pro- cessing elements, but each proc essing element operates on different data this architecture is efficient at executing math intensive dsp algorithms entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file table 1. adsp-21261 benchmarks (at 150 mhz) benchmark algorithm speed (at 150 mhz) 1024 point complex fft (radix 4, with reversal) 61.3 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 3.3 ns iir filter (per biquad) 1 13.3 ns matrix multiply (pipelined) [33] [31] [44] [41] 30 ns 53.3 ns divide (y/) 20 ns inverse square root 30 ns
adsp-21261 preliminary technical data rev. prb | page 5 of 44 | june 2004 independent, parallel computation units within each processing element is a set of computational units the computational units consist of an arithmeticlogic unit (alu), multiplier and shifter these units perform all opera- tions in a single cycle the thre e units within each processing element are arranged in paralle l, maximiing computational throughput single multifunctio n instructions execute parallel alu and multiplier operations in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments these computation unit s support ieee -bit single- precision floating-point, -bit extended precision floating- point, and -bit fixed-point data formats data register file a general-purpose data register file is contained in each pro- cessing element the register fi les transfer data between the computation units and the data buses, and store intermediate results these -port, -regist er ( primary, secondary) register files, combined with the adsp-x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory the registers in pe are referred to as r-r and in pe as s-s single-cycle fetch of instruction and four operands the adsp- features an enhanc ed harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see the figure on page ) with the adsp-s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instructio n (from the cache), all in a sin- gle cycle instruction cache the adsp- includes an on-c hip instruction cache that enables three-bus operation for fe tching an instruction and four data values the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing data address generators with zero-overhead hardware circular buffer support the adsp-s two data addr ess generators (dags) are used for indirect addressing and implementing circular data buffers in hardware circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are common ly used in digi tal filters and figure adsp- system sample configuration dai sport sport sport sport spo rt sport scl sda sfs sdb sru dai_p dai_p dai_p da i_p da i_p dai_p dac (optioal) adc (optioal) fs cl sdat fs cl sdat cloc fl a g - cl i tal cl_cfg- boo t cf g - addr parallel port ram, rom boot rom io de ice oe dt we rd wr out e d-0 t reset t dsp- 22 ddress dt otro s 0 p p s
rev. prb | page 6 of 44 | june 2004 adsp-21261 preliminary technical data fourier transforms. the two dags of th e adsp-21261 contain sufficient registers to allow the creation of up to 32 circular buff- ers (16 primary register se ts, 16 secondary). the dags automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the adsp-21261 can conditionally exec ute a multiply, an add, and a subtract in both processing elements while branching, and fetching up to four 32-bit valu es from memory?all in a single instruction. adsp-21261 memory and i/o interface features the adsp-21261 adds the following architectural features to the simd sharc family core. dual-ported on-chip memory the adsp-21261 contains one mega bit of internal sram and three megabits of internal mask-programmable rom. each block can be configured for diffe rent combinations of code and data storage (see figure 3 on page 7 ). each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o proc essor. the dual-ported memory, in com- bination with three separate on-chip buses, allow two data transfers from the core and one fr om the i/o processor, in a sin- gle cycle. the adsp-21261?s sram can be co nfigured as a maximum of 32k words of 32-bit data, 64k word s of 16-bit data, 21.3k words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to one megabi t. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit float- ing-point storage format is suppo rted that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one dedicated to each memory block assures single-cyc le execution with two data transfers. in this case, the inst ruction must be available in the cache. dma controller the adsp-21261?s on-chip dma co ntroller allows zero-over- head data transfers without pr ocessor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simul- taneously executing its progra m instructions. dma transfers can occur between the adsp-21261? s internal memory and its serial ports, the spi-compatible (serial peripheral interface) port, the idp (input data port), parallel data ac quisition port (pdap) or the parallel port. 18 channels of dma are available on the adsp-21261?one for the sp i interface, twelve via the serial ports, four via the input data port and one via the proces- sor?s parallel port. programs ca n be downloaded to the adsp- 21261 using dma transfers. other dma features include inter- rupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. digital audio interface (dai) the digital audio interface (dai) provides the ability to con- nect various peripherals to any of the dsps 20 dai pins (dai_p[20:1]). programs make these connecti ons using the signal routing unit (sru, shown in figure 1 ). the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. this provides easy use of the dai associated peripherals for a much wider variety of applica- tions by using a larger set of al gorithms than is possible with nonconfigurable signal paths. the dai also includes four serial ports, two precision clock gen- erators (pcgs), an input data po rt (idp), six flag outputs and six flag inputs, and three timers. the idp provides an additional input path to the dsp core configurable as either eight channels of i 2 s or serial data, or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independent from the adsp-21261's serial ports. for complete information on using the dai, see the adsp- 2126x sharc dsp peripherals manual serial ports the adsp-21261 features six snchr onous serial ports that pro- vie an inexpensive interface to a ie variet of igital an mixe-signal peripheral evices such as analog devices ad18x famil of auio coecs dacs or adcs the serial ports are mae up of to ata lines a cloc an frame snc the ata lines can e programme to either transmit or receive an each ata line has its on eicate dma channel serial ports are enale via 12 programmale an simultaneous receive or transmit pins that support up to 2 transmit or 2 receive channels of serial a ta hen all four sprts are enale or four full uplex tdm streams of 128 channels per frame the serial ports operate at up to one-uarter of the dsp core cloc rate proviing each i th a maximum ata rate of m its for a 1 mh core seri al port ata can e automat- icall transferre to an from on-chip memor via eicate dma channels each of the serial ports can or in conunction ith another serial port to provie tdm support ne sprt provies to transmit signals hile the other sprt provies the to receive signals the fr ame snc an cloc are share
adsp-21261 preliminary technical data rev. prb | page 7 of 44 | june 2004 figure 3. adsp-21261 memory map reserved 0x0004 2000 - 0x0005 7fff block 0 rom (1.5m bit) 0x0005 8000 - 0x0002 ffff iop registers 0x0000 0000 - 0x0003 ffff block 0 sram (0.5m bit) 0x0004 0000 - 0x0004 1fff reserved 0x0005 3000 - 0x0005 ffff block 1 sram (0.5m bit) 0x0006 0000 - 0x0006 1fff block 1 rom (1.5m bit) 0x0007 8000 - 0x0007 dfff reserved 0x0007 e000 - 0x0007 ffff reserved 0x0006 2000 - 0x0007 7fff long word addressing reserved 0x0008 4000 - 0x000a ffff block 0 rom ( 1.5m bit) 2 0x000b 0000 - 0x000b bfff iop registers 0x0000 0000 - 0x0003 ffff block 0 sram (0.5m bit) 0x0008 0000 - 0x0008 3fff reserved 0x000b c000 - 0x000b ffff block 1 sram (0.5m bit) 0x000c 0000 - 0x000c 3fff block 1 rom (1.5m bit) 3 0x000f 0000 - 0x000f bfff reserved 0x000f c000 - 0x000f ffff reserved 0x000c 4000 - 0x000e ffff normal word addressing reserved 0x0010 8000 - 0x0015 ffff block 0 rom (1.5m bit) 0x0016 0000 - 0x0017 7fff iop registers 0x0000 0000 - 0x0003 ffff block 0 sram (0.5m bit) 0x0010 0000 - 0x0010 7fff reserved 0x0017 8fff - 0x0017 ffff block 1 sram (0.5m bit) 0x0018 0000 - 0x0018 7fff block 1 rom (1.5m bit) 0x001e 0000 - 0x001f 7fff reserved 0x0018 8000 - 0x001d ffff short word addressing reserved 0x0020 0000 - 0x00ff ffff external dma address space 1 0x0100 0000 - 0x02ff ffff reserved 0x0300 0000 - 0x3fff ffff external memory space 1 external memory is not directly accessible by the core. dma must be used to read or writ e to this memory using the spi or parallel port. 2 block 0 rom has a 48-bit address range (0xa0000?0xa7 fff). 3 block 1 rom has a 48-bit address range (0xe0000?0xe7 fff). internal memory space reserved 0x000
rev. prb | page 8 of 44 | june 2004 adsp-21261 preliminary technical data serial ports operate in four modes: standard dsp serial mode multichannel (tdm) mode i 2 s mode left-justified sample pair mode left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitte d/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry standard interface com- monly used by audio codecs, adcs and dacs), with two data pins, allowing four left-jus tified sample pair or i 2 s channels (using two stereo devices) per se rial port, with a maximum of up to 24 audio channels. the serial ports permit little-endian or big-endian transmissi on formats and word lengths selectable from 3 bits to 32 bits. for the le ft-justified samp le pair and i 2 s modes, data-word lengths are selectable between 8 bits and 32 bits. serial ports offer selectab le synchronization and transmit modes as well as optional serial peripheral (compatible) interface serial peripheral interface (spi) is an industry standard syn- chronous serial link, enabling the adsp- spi compatible port to communicate with other spi compatible devices spi is an interface consisting of two data pins, one device select pin, and one clock pin it is a full-duplex synchronous serial inter- face, supporting both master an d slave modes the spi port can operate in a multimaster environment by interfacing with up to four other spi compatible devices, either acting as a master or slave device the adsp- spi compatible peripheral imple- mentation also features programmable baud rates up to mh, clock phases, and polarities the adsp- spi compatible port uses open drain drivers to support a multimas- ter configuration and to avoid data contention parallel port the parallel port prov ides interfaces to sram and peripheral devices the multiplexed address and data pins (ad-) can access -bit devices with up to bits of address, or -bit devices with up to bits of ad dress in either mode, - or - bit, the maximum data transfer rate is one-third the core clock speed as an example, for a clock rate of mh, this is equiv- alent to m bytesec dma transfers are used to move data to and from internal memory access to the core is also facilitated through the paral- lel port register readwrite functions the rd , wr , and ale (address latch enable) pins are the control pins for the parallel port timers the adsp- has a total of four timers a core timer able to generate periodic software inte rrupts and three general-purpose timers that can that can genera te periodic interrupts and be independently set to operat e in one of three modes pulse waveform generation mode pulse width countcapture mode external event watchdog mode the core timer can be configured to use flag as a timer expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation a -bit configuration register, a -bit count register, a -bit period register, and a - bit pulse width register a sin- gle control and status register enables or disables all three general-purpose timers independently rom based security the adsp- has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthoried reading from the internal code when enabled when using this feature, the ds p does not boot-load any exter- nal code, executing exclusively from internal sramrom additionally, the dsp is not freel y accessible via the jtag port instead, a unique -bit key, wh ich must be scanned in through the jtag or test access port will be assigned to each customer the device will ignore a wrong key emulation features and external boot modes are only available after the correct key is scanned program booting the internal memory of the adsp- boots at system power-up from an -bit eprom via the parallel port, an spi master, an spi slave or an intern al boot booting is determined by the boot configuration (b ootcfg-) pins selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin executing from rom phase-locked loop the adsp- uses an on-chip phase-locked loop (pll) to generate the internal clock for the core on power up, the clcfg- pins are used to select ratios of , , and after booting, numerous other ra tios can be selected via soft- ware control the ratios are made up of software configurable numerator values from to an d software configurable divi- sor values of , , , , and power supplies the adsp- has separate powe r supply connections for the internal ( ddit ), external ( ddet ), and analog (a dd a ss ) power supplies the internal and analog supplies must meet the requirement the external supply must meet the requirement all external supply pins must be connected to the same power supply ote that the analog supply (a dd ) powers the adsp-s clock generator pll to produce a stable clock, programs should provide an external circuit to filter the power input to
adsp-21261 preliminary technical data rev. prb | page 9 of 44 | june 2004 the a vdd pin. place the filter as clos e as possible to the pin. for an example circuit, see figure 4 . to prevent noise coupling, use a wide trace for the analog ground (a vss ) signal and install a decoupling capacitor as close as possible to the pin. note that the a vss and a vdd pins specified in figure 4 are inputs to the sharc and not the analog gr ound plane on the board. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test ac cess port of the adsp-21261 processor to monitor and contro l the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulat ion at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks. the processor s jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the adsp-21261 is supported with a complete set of crosscore tm software and hardware development tools, including analog devices emulators and visualdsp++ tm devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-21261. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the sharc has architectural features that impr ove the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the so ftware developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottleneck s in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: view mixed c/c++ and assembly code (interleaved source and object information) insert breakpoints set conditional breakpoints on registers, memory, and stacks trace instruction execution perform linear or statistical profiling of program execution fill, dump, and graphically plot the contents of memory perform source level debugging create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the sharc devel- opment tools, including the colo r syntax highlighting in the visualdsp++ editor. this capability permits programmers to: control how the development tools process inputs and generate outputs maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vd k also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a spec ific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology for cr eating, using, and reusing soft- ware components (independent modules of substantial functionality) to quickly and reli ably assemble so ftware applica- tions. download components from the web and drop them into figure 4. analog power (a vdd ) filter circuit v ddint a vdd a vss 0.01 f 0.1 f 10
rev. prb | page 10 of 44 | june 2004 adsp-21261 preliminary technical data the application. publish component archives from within visualdsp++. vcse supports co mponent implementation in c/c++ or assembly language. use the expert linker to visua lly manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical fo rm, easily move code and data to different areas of the dsp or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the develo per to move between the graphi- cal and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in- circuit emulation is assured by the use of the processors jtag interfacethe emulator does not af fect target system loading or timing. the emulator uses the tap to access the internal fea- tures of the dsp, allowing th e developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halt ed to send data and commands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on sys- tem timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. additional information this data sheet provides a ge neral overview of the adsp-21261 architecture and functionality. for detailed information on the adsp-2126x family core architectu re and instruction set, refer to the adsp-2126x dsp core manual and the adsp-21160 sharc dsp instruction set reference.
adsp-21261 preliminary technical data rev. prb | page 11 of 44 | june 2004 pin function descriptions adsp-21261 pin definitions are list ed below. inputs identified as synchronous (s) must meet ti ming requirements with respect to clkin (or with respect to tc k for tms, tdi). inputs iden- tified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: dai_px, spiclk, miso, mosi, emu , tms,trst , tdi, and ad15-0 (note: these pins have pull-up resistors.) the following symbol s appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state. table 2. pin descriptions pin type state during and after reset function ad15-0 i/o/t three-state with pull-up enabled parallel port address/data. the adsp-21261 parallel port and its corresponding dma unit output addresses and data for pe ripherals on these multiplexed pins. the multiplex state is determined by the ale pi n. the parallel port can operate in either 8-bit or 16-bit mode. each ad pin has a 22.5 k ? internal pull-up resistor. see address data modes on page 14 for details of the ad pin operation: for 8-bit mode: ale is automatically asserted whenever a change occurs in the upper 16 external address bits, a23-8; ale is used in conjunction with an external latch to retain the values of the a23-8. for 16-bit mode: ale is automatically asserted whenever a change occurs in the address bits, a15-0; ale is used in conjunction with an external latch to retain the values of the a15-0. to use these pins as flags (flags15-0) set (=1) bit 20 of the sysctl register and disable the parallel port. when used as an input, the idp channel 0 can use these pins for parallel input data. rd o output only, driven high 1 parallel port read enable. rd is asserted low whenever the dsp reads 8-bit or 16-bit data from an external memory device. when ad15-0 are flags, this pin remains deasserted. wr o output only, driven high 1 parallel port write enable. wr is asserted low whenever the dsp writes 8-bit or 16-bit data to an external memory device. when ad15-0 are flags, this pin remains deasserted. ale o output only, driven low 1 parallel port address latch enable. ale is asserted whenever the dsp drives a new address on the parallel port address pins. on re set, ale is active high. however, it can be reconfigured using software to be active low. when ad15-0 are flags, this pin remains deasserted. flag3-0 i/o/a three-state flag pins. each flag pin is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. these pins can be used as an spi interface slave select output during spi mastering. these pins are also multiplexed with the irqx and the timexp signals. in spi master boot mode, flag0 is the slave se lect pin that must be connected to an spi eprom. flag0 is configured as a slave select du ring spi master boot. when bit 16 is set (=1) in the sysctl register, flag0 is configured as irq0 . when bit 17 is set (=1) in the sysctl register, flag1 is configured as irq1 . when bit 18 is set (=1) in the sysctl register, flag2 is configured as irq2 . when bit 19 is set (=1) in the sysctl regi ster, flag3 is configured as timexp, which indicates that the system timer has expired.
rev. prb | page 12 of 44 | june 2004 adsp-21261 preliminary technical data dai_p20-1 i/o/t three-state with programmable pull- up digital audio interface pins . these pins provide the physical interface to the sru. the sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to th e pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the sru may be routed to any of these pins. the sru provides the connection from the serial ports, input data port, precision clock generators, and timer to the dai_p20-1 pins. these pins have internal 22.5 k ? pull- up resistors which are enabled on reset. these pull-ups can be disabled in the dai_pin_pullup register. spiclk i/o three-state with pull-up enabled serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bi t transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select input is driven inactive (high). spiclk is used to shift out and shift in the data dr iven on the miso and mosi lines. the data is always shifted out on one clock edge and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. sp iclk has a 22.5 k ? internal pull-up resistor. spids i input only serial peripheral interface slave device select . an active low signal used to select the dsp as an spi slave device. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode the dsps spids signal can be driven by a slave device to signal to the dsp (as spi master) that an error has occurred, as some other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single-master, multiple-slave configur ation where flag pins are used, this pin must be tied or pulled high to v ddext on the master device. for adsp-21261 to adsp- 21261 spi interaction, any of the master adsp-21261's flag pins can be used to drive the spids signal on the adsp-21261 spi slave device. mosi i/o (o/d) three-state with pull-up enabled spi master out slave in . if the adsp-21261 is configured as a master, the mosi pin becomes a data transmit (output) pin, tran smitting output data. if the adsp-21261 is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in an adsp-21261 spi interconnection, the data is shifted out from the mosi output pin of the master and shifted into the mosi input(s) of the slave(s). mosi has a 22.5 k ? internal pull-up resistor. miso i/o (o/d) three-state with pull-up enabled spi master in slave out . if the adsp-21261 is configured as a master, the miso pin becomes a data receive (input) pin, rece iving input data. if the adsp-21261 is configured as a slave, the miso pin beco mes a data transmit (output) pin, trans- mitting output data. in an adsp-21261 spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has a 22.5 k ? internal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. to enable broadcast transmission to multiple spi-slaves, the ds p's miso pin may be disabled by setting (=1) bit 5 (dmiso) of the spictl register. bootcfg1-0 i input only boot configuration select . selects the boot mode for the dsp. the bootcfg pins must be valid before reset is asserted. see table 4 on page 14 for a description of the boot modes. table 2. pin descriptions (continued) pin type state during and after reset function
adsp-21261 preliminary technical data rev. prb | page 13 of 44 | june 2004 clkin i input only local clock in . used in conjunction with xtal. clkin is the adsp-21261 clock input. it configures the adsp-21261 to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-21261 to use the external clock source such as an external clock oscillator. the core is clocked either by the pll output or this clock input depending on the clkcfg1-0 pin sett ings. clkin may not be halted, changed, or operated below the specified frequency. xtal o output only 2 crystal oscillator terminal . used in conjunction with clkin to drive an external crystal. clkcfg1-0 i input only core/clkin ratio control . these pins set the start up clock frequency. see table 5 on page 14 for a description of the clock configuration modes. note that the operating frequency can be changed by programming the pll multi- plier and divider in the pmctl register at any time after the core comes out of reset. rstout /clkout o output only reset out/local clock out . drives out the core reset signal to an external device. clkout can also be configured as a reset out pin (rstout) . the functionality can be switched between the pll output clock and re set out by setting bit 12 of the pmctl register. the default is reset out. reset i/a input only processor reset . resets the adsp-21261 to a know n state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i input only 3 test clock (jtag) . provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21261. tms i/s three-state with pull-up enabled test mode select (jtag) . used to control the test state machine. tms has a 22.5 k ? internal pull-up resistor. tdi i/s three-state with pull-up enabled test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 22.5 k ? internal pull-up resistor. tdo o three-state 4 test data output (jtag) . serial scan output of the boundary scan path. trst i/a three-state with pull-up enabled test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for prope r operation of th e adsp-21261. trst has a 22.5 k ? internal pull-up resistor. emu o (o/d) three-state with pull-up enabled emulation status . must be connected to the adsp-21261 analog devices dsp tools product line of jtag emulators target board connector only. emu has a 22.5 k ? internal pullup resistor. v ddint p core power supply . nominally +1.2 v dc and suppl ies the dsps co re processor (13 pins on the bga package, 32 pins on the lqfp package). v ddext p i/o power supply . nominally +3.3 v dc. (6 pins on the bga package, 10 pins on the lqfp package). a vdd p analog power supply . nominally +1.2 v dc and supplies the dsps internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 8. a vss g analog power supply return . gnd g power supply return . (54 pins on the bga package, 39 pins on the lqfp package). 1 rd , wr , and ale are continuously driven by the dsp and will not be three-stated. 2 output only is a three-state driver wi th its output path always enabled. 3 input only is a three-state driver with both output paths and pull-up disabled. 4 three-state is a three-state driver, with pull-up disabled table 2. pin descriptions (continued) pin type state during and after reset function
rev. prb | page 14 of 44 | june 2004 adsp-21261 preliminary technical data address data pins as flags to use these pins as flags (fla gs15-0) set (=1) bit 20 of the sysctl register and di sable the parallel port. boot modes core instruction rate to clkin ratio modes address data modes the following table shows the func tionality of the ad pins for 8-bit and 16-bit transfers to the parallel port. for 8-bit data transfers, ale latches address bi ts a23-a8 when asserted, fol- lowed by address bits a7-a0 and data bits d7-d0 when deasserted. for 16-bit data transf ers, ale latches address bits a15-a0 when asserted, followed by data bits d15-d0 when deasserted. table 3. ad[15:0] to flag pin mapping ad pin flag pin ad0 flag8 ad1 flag9 ad2 flag10 ad3 flag11 ad4 flag12 ad5 flag13 ad6 flag14 ad7 flag15 ad8 flag0 ad9 flag1 ad10 flag2 ad11 flag3 ad12 flag4 ad13 flag5 ad14 flag6 ad15 flag7 table 4. boot mode selection bootcfg1-0 booting mode 00 spi slave boot 01 spi master boot 10 parallel port boot via eprom 11 internal boot mode (rom code only) table 5. core instruction rate/ clkin ratio selection clkcfg1-0 core to clkin ratio 00 3:1 01 16:1 10 8:1 11 reserved table 6. address/ data mode selection ep data mode ale ad7-0 function ad15-8 function 8-bit asserted a15-8 a23-16 8-bit deasserted d7-0 a7-0 16-bit asserted a7-0 a15-8 16-bit deasserted d7-0 d15-8
adsp-21261 preliminary technical data rev. prb | page 15 of 44 | june 2004 adsp-21261 specifications recommended operating conditions electrical characteristics absolute maximum ratings parameter 1 1 specifications subject to change without notice. min max unit v ddint internal (core) supply voltage 1.14 1.26 v a vdd analog (pll) supply voltage 1.14 1.26 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih high level input voltage 2 , @ v ddext = max 2 applies to input and bid irectional pins: ad15-0, flag3-0, dai_px, spiclk, mosi, miso, spids , bootcfgx, clkcfgx, reset , tck, tms, tdi, trst . 2.0 v ddext + 0.5 v v il low level input voltage 2 @ v ddext = min C0.5 +0.8 v v ih_clkin high level input voltage 3 , @ v ddext = max 3 applies to input pin clkin. 1.74 v ddext + 0.5 v v il_clkin low level input voltage, @ v ddext = min C0.5 +1.19 v t amb ambient operating temperature 4, 5 4 see thermal characteristics on page 38 for information on th ermal specifications. 5 see engineer-to-engineer note (no. 216) for further information. 0+70 c parameter 1 test conditions min max unit v oh high level output voltage 2 @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol low level output voltage 2 @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih high level input current 4, 5 @ v ddext = max, v in = v ddext max 10 a i il low level input current 4 @ v ddext = max, v in = 0 v 10 a i ilpu low level input current pull-up 5 @ v ddext = max, v in = 0 v 200 a i ozh three-state leakage current 6, 7, 8 @ v ddext = max, v in = v ddext max 10 a i ozl three-state leakage current 6 @ v ddext = max, v in = 0 v 10 a i ozlpu three-state leakage current pull-up 7 @ v ddext = max, v in = 0 v 200 a i dd-intyp supply current (internal) 9, 10, 11 t cclk = 6.67 ns, v ddint = 1.2 v, t amb = +25 c375ma ai dd supply current (analog) 12 a vdd = max 10 ma c in input capacitance 13, 14 f in = 1 mhz, t case = 25c, v in = 1.2 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidir ectional pins: ad15-0, rd , wr , ale, flag3-0, dai_px, spiclk, mosi, miso, emu , tdo, clkout, xtal. 3 see output drive currents on page 37 for typical drive current capabilities. 4 applies to input pins: spids , bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with 22.5 k ? ? ( ) internal (core) supply voltage (v ddint ) 1 C0.3 v to +1.4 v analog (pll) supply voltage (a vdd ) 1 C0.3 v to +1.4 v external (i/o) supply voltage (v ddext ) 1 C0.3 v to +3.8 v input voltage C0.5 v to v ddext 1 + 0.5 v
rev. prb | page 16 of 44 | june 2004 adsp-21261 preliminary technical data esd sensitivity timing specifications the adsp-21261s internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, serial ports, and parallel po rt (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the dsps internal clock frequency and exter- nal (clkin) clock frequency with the clkcfg1-0 pins. to determine switching frequencies for the serial ports, divide down the internal clock, usin g the programmable divider con- trol of each port (divx for the serial ports). the adsp-21261s intern al clock switches at higher frequencies than the system input clock (clk in). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsps internal clock (the clock source for the parallel po rt logic and i/o pads). note the definitions of various clock periods that are a function of clkin and the appropriate ratio control ( table 7 ). figure 5 shows core to clkin ratios of 3:1, 8:1, and 16:1 with external oscillator or cr ystal. note that more ratios are possible and can be set through software using the power management control register (pmctl). for more information, see the adsp- 2126x sharc dsp core manual . use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add paramete rs to derive longer times. see figure 30 on page 37 under test conditions for voltage ref- erence levels. switching characteristics specif y how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given output voltage swing C0.5 v to v ddext 1 + 0.5 v load capacitance 1 200 pf storage temperature range 1 C65 c to +150 c junction temperature under bias 125 c 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greate r than those indicated in the operational sections of this sp ecification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equi pment and can discharge without detection. although the adsp-21261 feat ures proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 7. adsp-21261 clkout and cclk clock genera- tion operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk timing requirements description 1 t ck clkin clock period t cclk (processor) core clock period t sclk serial port clock period = (t cclk ) sr t spiclk spi clock period = (t cclk ) spir 1 where: sr = serial port-to-core clock ratio (wide range, determined by sport clkdiv) spir = spi-to-core clock ratio (wide range, determined by spibaud register) dai_px = serial port clock spiclk = spi clock figure 5. core clock and system clock relationship to clkin clkin cclk (core clock) plliclk xtal xtal osc pll 3:1, 8:1, 16:1 clkout clk-cfg [1:0]
adsp-21261 preliminary technical data rev. prb | page 17 of 44 | june 2004 circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to si gnals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. the adsp-21261s internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, serial ports, and parallel po rt (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the dsps internal clock frequency and exter- nal (clkin) clock frequency with the clkcfg1-0 pins. to determine switching frequencies for the serial ports, divide down the internal clock, usin g the programmable divider con- trol of each port (divx for the serial ports). the adsp-21261s intern al clock switches at higher frequencies than the system input clock (clk in). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsps internal clock (the clock source for the parallel po rt logic and i/o pads). note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control.
rev. prb | page 18 of 44 | june 2004 adsp-21261 preliminary technical data power-up sequencing the timing requirements fo r dsp startup are given in table table 8. power-up sequencing timing requirements (dsp startup) name parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext -50 200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 200 ms t clkrst 2 clkin valid before reset deasserted 10 s t pllrst 3 pll control setup before reset deasserted 20 s t wrst 4 subsequent reset low pulse width 4t ck ns switching characteristic t corerst 4, 5 dsp core reset deasserted after reset deasserted 4096t ck 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. voltage ra mp rates can vary from microseconds to h undreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to the crystal oscillator manufacturer's data sheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin and internal oscill ator circuit in conjunction with an ext ernal crystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 10 . if setup time is not met, 1 additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing clkin reset rstdd rstout* ddet ddit prst rst dd iddedd -0 orerst *utipeed wit out
adsp-21261 preliminary technical data rev. prb | page 19 of 44 | june 2004 clock input clock signals the adsp- can use an external clock or a crystal see cli pin description the pr ogrammer can configure the adsp- to use its internal clock generator by connecting the necessary components to cli and tal figure shows the component connections used for a crystal operating in fun- damental mode ote that the clock rate is achieved using a mh crystal and a pll multiplier ratio (cclcli) table 9. clock input parameter min max unit timing requirements t ck 1 clkin period 20 160 2 ns t ckl 1 clkin width low 8.5 80 2 ns t ckh 1 clkin width high 8.5 80 2 ns t ckrf clkin rise/fall (0.4 v C 2.0 v) 3 ns t cclk cclk period 3 6.67 10 ns 1 applies only for clkcfg1-0 = 00 and defa ult values for pll control bits in pmctl. 2 applies only for clkcfg1-0 = 01 and defa ult values for pll control bits in pmctl. 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . figure 7. clock input clkin t ck t ckh t ckl figure 8. 150 mhz operation with a 9.375 mhz fundamental mode crystal clkin xtal c1 c2 x1 note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. crystal selection must comply with clkcfg1-0 = 10 or = 01. 1m
rev. prb | page 20 of 44 | june 2004 adsp-21261 preliminary technical data reset interrupts the following timing specification applies to the flag, flag, and flag pins when they are config ured as ir , ir , and ir interrupts also applies to dai_p pins when configured as interrupts core timer the following timing specification applies to flag when it is configured as the core timer (ctimer) table 10. reset parameter min max unit timing requirements t wrst reset pulse width low 1 1 applies after the power-up sequence is comp lete. at power-up, the processor's internal ph ase-locked loop requires no more than 1 00 () 4t ck ns t srst reset setup before clkin low 8 ns figure 9. reset clkin reset wrst srst table 11. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t cclk + 2 ns figure 10. interrupts dai_p20-1 (flag2-0) (irq2-0) ipw table 12. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 4 t cclk C 1 ns figure 11. core timer flag3 (ctimer) t wctim
adsp-21261 preliminary technical data rev. prb | page 21 of 44 | june 2004 timer pwm_out cycle timing the following timing specification applies to timer in pwm_out (pulse width modulati on) mode timer signals are routed to the dai_p pins through the sru therefore, the timing specifications provided below are valid at the dai_p pins timer wdth_cap timing the following timing specification applies to timer in wdth_cap (pulse width count and capture) mode timer sig- nals are routed to the dai_p pins through the sru therefore, the timing specificatio ns provided below are valid at the dai_p pins table 13. timer[2:0] pwm_out timing parameter min max unit switching characteristic t pwmo timer[2:0] pulse width output 2 t cclk C 1 2(2 31 C 1) t cclk ns figure 12. timer[2 :0] pwm_out timing dai_p[20:1] (timer[2:0]) t pwmo table 14. timer[2:0] width capture timing parameter min max unit timing requirement t pwi timer[2:0] pulse width 2 t cclk 2(2 31 C 1) t cclk ns figure 13. timer[2:0] width capture timing dai_p[20:1] (timer[2:0]) t pwi
rev. prb | page 22 of 44 | june 2004 adsp-21261 preliminary technical data dai pin to pin direct routing for direct pin connections only (for example dai_pb_i to dai_pb_o) table 15. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 14. dai pin to pin direct routing dai_pn t dpio dai_pm
adsp-21261 preliminary technical data rev. prb | page 23 of 44 | june 2004 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins for the other ca ses, where the pcgs inputs and outputs are not directly routed tofrom dai pins (via pin buffers) there is not timing data available all timing param- eters and switching characteristics apply to external dai pins (dai_p C dai_p) table 16. precision clock generator (direct pin routing) parameter min max unit timing requirement t pcgiw input clock period 20 t strig pcg trigger setup before falling edge of pcg input clock 2 ns t htrig pcg trigger hold after falling edge of pcg input clock 2 ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrig pcg output clock and frame sync delay after pcg trigger 2.5 + 2.5 t pcgow 10 + 2.5 t pcgow ns t pcgow output clock period 40 figure 15. precision clock generator (direct pin routing) dai_pn pcg_trigx_i t strig dai_pm pcg_extx_i (clkin) dai_py pcg_clkx_o dai_pz pcg_fsx_o t htrig t dpcgio t dtrig t pcgiw t pcgow
rev. prb | page 24 of 44 | june 2004 adsp-21261 preliminary technical data flags the timing specifications provided below apply to the flag and dai_p pins, the parallel port, and the serial peripheral interface (spi) see table on page for more information on flag use table 17. flags parameter min max unit timing requirement t fipw flag[3:0] in pulse width 2 t cclk + 3 ns switching characteristic t fopw flag[3:0] out pulse width 2 t cclk C 1 ns figure 16. flags dai_p[20:1] (flag3-0 in ) (ad[15:0]) t fipw dai_p[20:1] (flag3-0 out ) (ad[15:0]) t fopw
adsp-21261 preliminary technical data rev. prb | page 25 of 44 | june 2004 memory readCparallel port use these specifications for asynchronous interfacing to memories (and memory-mappe d peripherals) when the adsp- is accessing external memory space table 18. 8-bit memory read cycle parameter min max unit timing requirements t drs address/data [7:0] setup before rd high 3.3 ns t drh address/data [7:0] hold after rd high 0 ns t dad address [15:8] to data valid d + 0.5 t cclk C 3.5 ns switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data [15:0] setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data [15:0] hold after ale deasserted 1 0.5 t cclk C 0.8 ns t alehz ale deasserted 1 to address/data[7:0] in high z 0.5 t cclk C 0.8 0.5 t cclk + 2.0 ns t rw rd pulse width d C 2 ns t adrh address/data [15:8] hold after rd high 0.5 t cclk C 1 + h ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by software to be active low. figure 17. read cycle for 8-bit memory timing valid data ad[15:8 ] valid address valid address t adas valid address ad[7:0] t alew ale rd rw wr d dr e drs dr dd erw
rev. prb | page 26 of 44 | june 2004 adsp-21261 preliminary technical data table 19. 16-bit memory read cycle parameter min max unit timing requirements t drs address/data [15:0] setup before rd high 3.3 ns t drh address/data [15:0] hold after rd high 0 ns switching characteristics ns t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data [15:0] setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data [15:0] hold after ale deasserted 1 0.5 t cclk C 0.8 ns t alehz ale deasserted 1 to address/data[15:0] in high z 0.5 t cclk C 0.8 0.5t cclk + 2.0 ns t rw rd pulse width d C 2 ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by so ftware to be active low. figure 18. read cycle for 16-bit memory timing valid address valid data t adas t adah ad[15:0] t alehz t drs t drh t alew ale rd rw wr erw
adsp-21261 preliminary technical data rev. prb | page 27 of 44 | june 2004 memory writeparallel port use these specifications for asynchronous interfacing to memories (and memory-mappe d peripherals) when the adsp- is accessing external memory space table 20. 8-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data [15:0] setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data [15:0] hold after ale deasserted 1 0.5 t cclk C 0.8 ns t ww wr pulse width d C 2 ns t adwl address/data [15:8] to wr low 0.5 t cclk C 1.5 ns t adwh address/data [15:8] hold after wr high 0.5 t cclk C 1 + h ns t alehz ale deasserted 1 to address/data[15:0] in high z 0.5 t cclk C 0.8 0.5t cclk + 2.0 ns t dws address/data [7:0] setup before wr high d ns t dwh address/data [7:0] hold after wr high 0.5 t cclk C 1.5 + h ns t dawh address/data to wr high d ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by software to be active low. figure 19. write cycle for 8-bit memory timing ad[15:8 ] valid address valid address t adas ad[7:0] t alew ale rd ww wr d dw dw e id dt dws dw id ddress dw erw
rev. prb | page 28 of 44 | june 2004 adsp-21261 preliminary technical data table 21. 16-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data [15:0] setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data [15:0] hold after ale deasserted 1 0.5 t cclk C 0.8 ns t ww wr pulse width d C 2 ns t alehz ale deasserted 1 to address/data[15:0] in high z 0.5 t cclk C0.8 0.5t cclk + 2.0 ns t dws address/data [15:0] setup before wr high d ns t dwh address/data [15:0] hold after wr high 0.5 t cclk C 1.5 + h ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by so ftware to be active low. figure 20. write cycle for 16-bit memory timing valid address valid data t adas ad[15:0] t alew ale wr ww rd d dw dws e erw
adsp-21261 preliminary technical data rev. prb | page 29 of 44 | june 2004 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed ) frame sync delay and frame sync setup and hold, ) data delay and data setup and hold, and ) scl width serial port signals (scl, fs , dxa,dxb) are routed to the dai_p pins using the sru therefore, the timing specifi- cations provided below are va lid at the dai_p pins table 22. serial portsexternal clock parameter min max unit timing requirements t sfse fs setup before sclk (externally generated fs in either transmit or receive mode) 1 2.5 ns t hfse fs hold after sclk (externally generated fs in either transmit or receive mode) 1 2.5 ns t sdre receive data setup before receive sclk 1 2.5 ns t hdre receive data hold after sclk 1 2.5 ns t sclkw sclk width 7 ns t sclk sclk period 20 ns switching characteristics t dfse fs delay after sclk (internally generated fs in either transmit or receive mode) 2 7ns t hofse fs hold after sclk (internally generated fs in either transmit or receive mode) 2 2ns t ddte transmit data delay after transmit sclk 2 7ns t hdte transmit data hold after transmit sclk 2 2ns 1 referenced to sample edge. 2 referenced to drive edge. table 23. serial portsinternal clock parameter min max unit timing requirements t sfsi fs setup before sclk (externally generated fs in either transmit or receive mode) 1 6ns t hfsi fs hold after sclk (externally generated fs in either transmit or receive mode) 1 1.5 ns t sdri receive data setup before sclk 1 6ns t hdri receive data hold after sclk 1 1.5 ns switching characteristics t dfsi fs delay after sclk (internally generated fs in transmit mode) 2 3ns t hofsi fs hold after sclk (internally generated fs in transmit mode) 2 C1.0 ns t dfsi fs delay after sclk (internally generated fs in receive or mode) 2 3ns t hofsi fs hold after sclk (internally generated fs in receive mode) 2 C1.0 ns t ddti transmit data delay after sclk 2 3ns t hdti transmit data hold after sclk 2 C1.0 ns t sclkiw transmit or receive sclk width 0.5t sclk C 2 0.5t sclk + 2 ns 1 referenced to the sample edge. 2 referenced to drive edge.
rev. prb | page 30 of 44 | june 2004 adsp-21261 preliminary technical data table 24. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit sclk 1 2ns t ddtte data disable from external transmit sclk 1 7ns t ddtin data enable from internal transmit sclk 1 C1 ns 1 referenced to drive edge. table 25. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 1 7ns t ddtenfs data enable for mce = 1, mfd = 0 1 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justified sample pair mode as well as dsp serial mode, and mce = 1, mfd = 0. figure 21. external late frame sync 1 1 this figure reflects changes made to su pport left-justified sample pair mode. drive sample drive dai_p[20:1] (sclk) dai_p[20:1] (fs) dai_p[20:1] (d x a/d x b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p[20:1] (sclk) dai_p[20:1] (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p[20:1] (d x a/d x b) note serial port signals (sclk, fs, dxa,/dxb) are routed to the dai_p[20:1] pins using the sru. the timing specifications provided here are valid at the dai_p[ 20:1] pins. t hfse/i
adsp-21261 preliminary technical data rev. prb | page 31 of 44 | june 2004 figure 22. serial ports drive edge dai_p[20:1] sclk (int) drive edge drive edge sclk dai_p[20:1] sclk (ext) t ddtte t ddten t ddtin dai_p[20:1] d x a/d x b dai_p[20:1] d x a/d x b dai_p[20:1] (sclk) dai_p[20:1] (fs) drive edge sample edge data receive internal clock data receive external clock drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p[20:1] (d x a/d x b) t ddti drive edge sample edge data transmit internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p[20:1] (sclk) dai_p[20:1] (fs) dai_p[20:1] (d x a/d x b) dai_p[20:1] (sclk) dai_p[20:1] (fs) dai_p[20:1] (d x a/d x b) dai_p[20:1] (sclk) dai_p[20:1] (fs) dai_p[20:1] (d x a/d x b)
rev. prb | page 32 of 44 | june 2004 adsp-21261 preliminary technical data input data port (idp) the timing requirements for the idp are given in table idp signals (scl, fs, sdata) are ro uted to the dai_p pins using the sru therefore, the ti ming specifications provided below are valid at th e dai_p pins table 26. input data port parameter min max unit timing requirements t sisfs fs setup before sclk rising edge 1 2.5 ns t sihfs fs hold after sclk rising edge 1 2.5 ns t sisd sdata setup before sclk rising edge 1 2.5 ns t sihd sdata hold after sclk rising edge 1 2.5 ns t idpclkw clock width 7 ns t idpclk clock period 20 ns 1 data, sclk, fs can come from any of the dai pins. sclk and fs ca n also come via the precision cl ock generators (pcg) or sports. pcg's input can be either clkin or any of the dai pins. figure 23. idp master timing dai_p[20:1] (sclk) dai_p[20:1] (fs) sample edge t sisd t sihd t sisfs t sihfs t idpclkw dai_p[20:1] (sdata)
adsp-21261 preliminary technical data rev. prb | page 33 of 44 | june 2004 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table pdap is the parallel mode operation of channel of the idp for details on the oper ation of the idp, see the idp chapter of the adsp-x peripherals manual ote that the most significant bits of external pdap data can be provided through either the parallel port ad or the dai_p pins the remaining bits can only be sourced through dai_p the timing below is valid at the dai_p pins or at the ad pins table 27. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken pdap_clken setup before pdap_clk sample edge 1 2.5 ns t hpclken pdap_clken hold after pdap_clk sample edge 1 2.5 ns t pdsd pdap_dat setup before sclk pdap_clk sample edge 1 2.5 ns t pdhd pdap_dat hold after sclk pdap_clk sample edge 1 2.5 ns t pdclkw clock width 7 ns t pdclk clock period 20 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t cclk ns t pdstrb pdap strobe pulse width 1 t cclk C 1 ns 1 source pins of data are addr[7:0], data[7:0], or dai pins. source pins for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 24. pdap timing dai_p[20:1] (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p[20:1] (pdap_clken) t pdstrb t pdhldd dai_p[20:1] (pdap_strobe)
rev. prb | page 34 of 44 | june 2004 adsp-21261 preliminary technical data spi interfacemaster table 28. spi interface protocol master switching and timing specifications parameter min max unit switching characteristics t spiclkm serial clock cycle 8 t cclk ns t spichm serial clock high period 4 t cclk C 2 ns t spiclm serial clock low period 4 t cclk C 2 ns t ddspidm spiclk edge to data out va lid (data out delay time) 3 ns t hdspidm spiclk edge to data out not valid (data out hold time) 10 ns t sdscim flag3-0 out (spi device select) low to first spiclk edge 4 t cclk C 2 ns t hdsm last spiclk edge to flag3-0 out high 4 t cclk C 1 ns t spitdm sequential transfer delay 4 t cclk C 1 ns timing requirements t sspidm data input valid to spiclk edge (data input setup time) 5 ns t hspidm spiclk last sampling edge to data input not valid 2 ns figure 25. spi master timing lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 cphase = 0 t sdscim t sspidm
adsp-21261 preliminary technical data rev. prb | page 35 of 44 | june 2004 spi interfaceslave table 29. spi interface protocol slave switching and timing specifications parameter min max unit switching characteristics t dsoe spids assertion to data out active 0 5 ns t dsdhi spids deassertion to data high impedance 0 5 ns t ddspids spiclk edge to data out valid (data out delay time) 7.5 ns t hdspids spiclk edge to data out not va lid (data out hold time) 2 t cclk C 2 ns t dsov spids assertion to data out valid (cphase = 0) 5 t cclk + 2 ns timing requirements t spiclks serial clock cycle 4 t cclk ns t spichs serial clock high period 2 t cclk C 2 ns t spicls serial clock low period 2 t cclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t cclk + 1 2 t cclk + 1 ns ns t hds last spiclk edge to spids not asserted cphase = 0 2 t cclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t cclk ns figure 26. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (iput) spi (p 0) (iput) spi (p ) (iput) sdso spis spis spis spis ds spis sspids spids dsdi s id s s id dsoe ddspids iso (output) osi (iput) sspids s id s pse pse 0 sdppw dso dspids
rev. prb | page 36 of 44 | june 2004 adsp-21261 preliminary technical data jtag test access port and emulation table 30. jtag test access port and emulation parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck high 1 7ns t hsys system inputs hold after tck high 1 8ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys system outputs delay after tck low 2 10 ns 1 system inputs = ad15-0, spids , clkcfg1-0, reset , bootcfg1-0, miso, mosi, spiclk, dai_px, flag3-0 2 system outputs = miso, mosi, spiclk, dai_px, ad15-0, rd , wr , flag3-0, clkout, emu , ale. figure 27. ieee 11499.1 jtag test access port tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21261 preliminary technical data rev. prb | page 37 of 44 | june 2004 output drive currents figure 28 shows typical i-v characteri stics for the output driv- ers of the adsp-21261. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 9 on page 19 through table 30 on page 36 . these include output disable time, output enable time, and capacitive loading. timing is measured on signals wh en they cross the 1.5 v level as described in figure 30 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 29 ). figure 33 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 31 , figure 32 , and figure 33 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20 C 80, v = min) vs. load capacitance. figure 28. adsp-21261 typical drive figure 29. equivalent device loading for ac measurements (includes all fixtures) figure 30. voltage reference levels for ac measurements sweep (v ddext )voltage(v) -20 03.5 0.5 1 1.5 2 2.5 3 0 -40 -30 20 40 -10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, 70 c 3.3v, 25 c 3.47v, 0 c v oh 30 10 3.11v, 70 c 3.3v, 25 c 3.47v, 0 c 1.5v 30pf to output pin 50 input or output 1.5v 1.5v figure 31. typical output rise/fall time (20-80, v ddext = max) figure 32. typical output rise/fall time (20-80, v ddext = min) load capacitance (pf) 8.0 0 0 120 40 100 12.0 4.0 2.0 10.0 6.0 r i s e a n d f a l l t i m e s ( n s ) y = 0.0904x + 1.9426 y = 0.0722x + 1.4042 80 60 20 rise fall load capacitance (pf) 12 0120 20 40 60 80 100 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 y = 0.0915x + 2.2207 y = 0.0728x +1.6336 rise fall
rev. prb | page 38 of 44 | june 2004 adsp-21261 preliminary technical data environmental conditions the adsp-21261 processor is rate d for performance over the commercial temperature range, t amb = 0c to 70c. thermal characteristics table 31 and table 32 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies wi th jesd51-8. th e junction-to- case measurement complies wi th mil-std-883. all measure- ments use a 2s2p jedec test board. to determine the junction temper ature of the device while on the application pcb, use: where: t j = junction temperature 0 c t case = case temperature ( 0 c) measured at the top center of the package () () () ( ) j t pd () + = t j t a () + = table 31. thermal characteristics for 136-ball bga 1 1 the thermal characteristics values provid ed in this table are modeled values. parameter condition typical unit ja airflow = 0 m/s 28.2 c/w jma airflow = 1 m/s 24.4 c/w jma airflow = 2 m/s 23.3 c/w jb 20.1 c/w jc 7.0 c/w jt airflow = 0 m/s 0.1 c/w jmt airflow = 1 m/s 0.3 c/w jmt airflow = 2 m/s 0.4 c/w table 32. thermal characteristics for 144-lead lqfp 1 1 the thermal characteristics values provid ed in this table are modeled values. parameter condition typical unit ja airflow = 0 m/s 32.5 c/w jma airflow = 1 m/s 28.9 c/w jma airflow = 2 m/s 27.8 c/w jc 7.8 c/w jt airflow = 0 m/s 0.5 c/w jmt airflow = 1 m/s 0.8 c/w jmt airflow = 2 m/s 1.0 c/w
adsp-21261 preliminary technical data rev. prb | page 39 of 44 | june 2004 136-ball bga pin configurations the following table shows th e adsp-21261s pin names and their default function after reset (in parentheses). table 33. 136-ball bga pin assignments pin name bga pin no. pin name bga pin no. pin name bga pin no. pin name bga pin no. clkcfg0 a01 clkcfg1 b01 bootcfg1 c01 v ddint d01 xtal a02 gnd b02 bootcfg0 c02 gnd d02 tms a03 v ddext b03 gnd c03 gnd d04 tck a04 clkin b04 gnd c12 gnd d05 tdi a05 trst b05 gnd c13 gnd d06 clkout a06 a vss b06 v ddint c14 gnd d09 tdo a07 a vdd b07 gnd d10 emu a08 v ddext b08 gnd d11 mosi a09 spiclk b09 gnd d13 miso a10 reset b10 v ddint d14 spids a11 v ddint b11 v ddint a12 gnd b12 gnd a13 gnd b13 gnd a14 gnd b14 v ddint e01 flag1 f01 ad7 g01 ad6 h01 gnd e02 flag0 f02 v ddint g02 v ddext h02 gnd e04 gnd f04 v ddext g13 dai_p18 (sd5b) h13 gnd e05 gnd f05 dai_p19 (sclk45) g14 dai_p17 (sd5a) h14 gnd e06 gnd f06 gnd e09 gnd f09 gnd e10 gnd f10 gnd e11 gnd f11 gnd e13 flag2 f13 flag3 e14 dai_p20 (sfs45) f14
rev. prb | page 40 of 44 | june 2004 adsp-21261 preliminary technical data ad5 j01 ad3 k01 ad2 l01 ad0 m01 ad4 j02 v ddint k02 ad1 l02 wr m02 gnd j04 gnd k04 gnd l04 gnd m03 gnd j05 gnd k05 gnd l05 gnd m12 gnd j06 gnd k06 gnd l06 dai_p12 (sd3b) m13 gnd j09 gnd k09 gnd l09 dai_p13 (sclk23) m14 gnd j10 gnd k10 gnd l10 gnd j11 gnd k11 gnd l11 v ddint j13 gnd k13 gnd l13 dai_p16 (sd4b) j14 dai_p15 (sd4a) k14 dai_p14 (sfs23) l14 ad15 n01 ad14 p01 ale n02 ad13 p02 rd n03 ad12 p03 v ddint n04 ad11 p04 v ddext n05 ad10 p05 ad8 n06 ad9 p06 v ddint n07 dai_p1 (sd0a) p07 dai_p2 (sd0b) n08 dai_p3 (sclk0) p08 v ddext n09 dai_p5 (sd1a) p09 dai_p4 (sfs0) n10 dai_p6 (sd1b) p10 v ddint n11 dai_p7 (sclk1) p11 v ddint n12 dai_p8 (sfs1) p12 gnd n13 dai_p9 (sd2a) p13 dai_p10 sd2b) n14 dai_p11 (sd3a) p14 table 33. 136-ball bga pin assignments (continued) pin name bga pin no. pin name bga pin no. pin name bga pin no. pin name bga pin no.
adsp-21261 preliminary technical data rev. prb | page 41 of 44 | june 2004 figure 34. 136-ball bga pin assignments (bottom view, summary) a vss v ddint v ddext i/o signals a vdd gnd use the center block of ground pins to provide thermal pathways to your printed circuit boards ground plane. key 1 2 3 4 5 6 7 8 9 10 11 12 14 13 p n m l k j h g f e d c b a
rev. prb | page 42 of 44 | june 2004 adsp-21261 preliminary technical data 144-lead lqfp pin configurations the following table shows th e adsp-21261s pin names and their default function after reset (in parentheses). table 34. 144-lead lqfp pin assignments pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. v ddint 1v ddint 37 v ddext 73 gnd 109 clkcfg0 2 gnd 38 gnd 74 v ddint 110 clkcfg1 3 rd 39 v ddint 75 gnd 111 bootcfg0 4 ale 40 gnd 76 v ddint 112 bootcfg1 5 ad15 41 dai_p10 (sd2b) 77 gnd 113 gnd 6 ad14 42 dai_p11 (sd3a) 78 v ddint 114 v ddext 7 ad13 43 dai_p12 (sd3b) 79 gnd 115 gnd 8 gnd 44 dai_p13 (sclk23) 80 v ddext 116 v ddint 9v ddext 45 dai_p14 (sfs23) 81 gnd 117 gnd 10 ad12 46 dai_p15 (sd4a) 82 v ddint 118 v ddint 11 v ddint 47 v ddint 83 gnd 119 gnd 12 gnd 48 gnd 84 v ddint 120 v ddint 13 ad11 49 gnd 85 reset 121 gnd 14 ad10 50 dai_p16 (sd4b) 86 spids 122 flag0 15 ad9 51 dai_p17 (sd5a) 87 gnd 123 flag1 16 ad8 52 dai_p18 (sd5b) 88 v ddint 124 ad7 17 dai_p1 (sd0a) 53 dai_p19 (sclk45) 89 spiclk 125 gnd 18 v ddint 54 v ddint 90 miso 126 v ddint 19 gnd 55 gnd 91 mosi 127 gnd 20 dai_p2 (sd0b) 56 gnd 92 gnd 128 v ddext 21 dai_p3 (sclk0) 57 v ddext 93 v ddint 129 gnd 22 gnd 58 dai_p20 (sfs45) 94 v ddext 130 v ddint 23 v ddext 59 gnd 95 a vdd 131 ad6 24 v ddint 60 v ddint 96 a vss 132 ad5 25 gnd 61 flag2 97 gnd 133 ad4 26 dai_p4 (sfs0) 62 flag3 98 clkout 134 v ddint 27 dai_p5 (sd1a) 63 v ddint 99 emu 135 gnd 28 dai_p6 (sd1b) 64 gnd 100 tdo 136 ad3 29 dai_p7 (sclk1) 65 v ddint 101 tdi 137 ad2 30 v ddint 66 gnd 102 trst 138 v ddext 31 gnd 67 v ddint 103 tck 139 gnd 32 v ddint 68 gnd 104 tms 140 ad1 33 gnd 69 v ddint 105 gnd 141 ad0 34 dai_p8 (sfs1) 70 gnd 106 clkin 142 wr 35 dai_p9 (sd2a) 71 v ddint 107 xtal 143 v ddint 36 v ddint 72 v ddint 108 v ddext 144
adsp-21261 preliminary technical data rev. prb | page 43 of 44 | june 2004 package dimensions the adsp-21261 is available in a 136-ball chip scale (mini- bga) package and a 144-lead low profile quad flat (lqfp) package, as shown in figure 35 and figure 36 . figure 35. 136-ball chip scale package mini-bga (csp_bga) (bc-136) seating plane 1.31 1.21 1.10 0.25 min detail a 0.50 0.46 0.40 (ball diameter) detail a 1.70 max 1. dimensions are in milimeters (mm). 2. the actual position of the ball grid is within 0.150 mm of its ideal position relative to the package edges. 3. the actual position of each ball is within 0.08 mm of its ideal position relative to the ball grid. 4. compliant to jedec standard mo-205-ae, except for the ball diameter. 5. center dimensions are nominal. a b c d e f g h j k l m n p 10987654321 13 14 11 12 0.80 bsc typ 10.40 bsc sq pin a1 indicator bottom view top view 12.00 bsc sq 0.12 max (ball coplanarity) 0.80 bsc typ 0.80 bsc typ
rev. prb | page 44 of 44 | june 2004 adsp-21261 preliminary technical data 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. ordering guide figure 36. 144-lead lqfp (st-144) part number ambient temperature range instruction rate on-chip sram rom operating voltage package 1 1 bc indicates ball grid array package. st indicates low profile quad flat package. adsp-21261skbc-x 0 c to +70 c 150 mhz 1 mbit 3 mbit 1.2 int/3.3 ext v 136-ball bga adsp-21261skbcz-x 2 2 z = pb-free part. for more information about lead-free package of ferings, please visit www.analog.com. 0 c to +70 c 150 mhz 1 mbit 3 mbit 1.2 int/3.3 ext v 136-ball bga adsp-21261skstz-x 2 0 c to +70 c 150 mhz 1 mbit 3 mbit 1.2 int/3.3 ext v 144-lead lqfp seating plane 1.60 max 0.15 0.05 0.08 max (lead coplanarity) 1.45 1.40 1.35 0.27 0.22 0.17 typ 0.50 bsc typ (lead pitch) 1 36 37 73 72 108 144 109 top view (pins down) 22.00 bsc sq 20.00 bsc sq detail a detail a pin 1 indicator 0.75 0.60 typ 0.45 1. dimensions are in millimeters and comply with jedec standard ms-026-bfb. 2. actual position of each lead is within 0.08 ofitsidealposition,whenmeasuredinthe lateral direction. 3. center dimensions are nominal.

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